Design and Analysis of 16-bit pipelined subranging SAR ADC and TDC

Author(s)	Bakialakshmi D, Varsha J
Country	India
Abstract	Analog to digital converters plays an important role in medical and signal processing applications. This paper proposes a 16-bit time based analog to digital converter (ADC) architecture by combining SAR Analog to Digital Converter and Vernier Time to Digital Converter. SAR analog to digital Converter is best suited for low power, high resolution and moderate applications. Vernier Time to Digital Converter with a high resolution to increase the conversion gain of VTC. The SAR ADC and Vernier TDC are pipelined to increase the conversion speed and reduce the area, power dissipation significantly smaller. A 16-bit combined pipelining SAR ADC and Vernier TDC was designed and simulated in Tanner EDA Tool.
Keywords	Successive Approximation Register, Time to Digital Converter, Voltage to Time Converter.
Field	Engineering
Published In	Volume 6, Issue 2, March-April 2024
Published On	2024-03-15
Cite This	Design and Analysis of 16-bit pipelined subranging SAR ADC and TDC - Bakialakshmi D, Varsha J - IJFMR Volume 6, Issue 2, March-April 2024. DOI 10.36948/ijfmr.2024.v06i02.14872
DOI	https://doi.org/10.36948/ijfmr.2024.v06i02.14872
Short DOI	https://doi.org/gtmzs3

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