Design and Analysis of Phase Locked Loop

Author(s)	Arjun Patel, Bhavnil Patel
Country	-
Abstract	This paper focuses on the redesign of a PLL system using the 45nm CMOS technology (GPDK045library) in CADENCE Vertuoso Analog Design Environment. The proposed PLL architecture includes following modules: phase and frequency detector(PFD) to compare phase(or frequency) of input reference and phase(or frequency) of feedback is signal and generate the difference or an error signal, charge pump and loop filter is to convert the digital UP and DOWN signals into analog control voltage, voltage controlled oscillator is to produce the clock output which is the multiplication of the input reference frequency and multiplication factor(N) and frequency divider is to equal the output frequency with input frequency. All modules are integrated in order produce the 1 GHz output frequency from 4MHz input frequency at 1.8V DC supply and have lock time 40µs. Output clock have period jitter 44.87ps.
Keywords	Phase locked loop, charge pump, phase and frequency detector, voltage controlled oscillator and lock time.
Field	Engineering
Published In	Volume 1, Issue 1, July-August 2019
Published On	2019-07-16
Cite This	Design and Analysis of Phase Locked Loop - Arjun Patel, Bhavnil Patel - IJFMR Volume 1, Issue 1, July-August 2019.

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