Implementation of AES Algorithm

Author(s)	Aasawari Ujjainkar, A. B. Kharate
Country	India
Abstract	Now a day’s large number of internet and wireless communication users has led to an increasing demand of security measures and devices for protecting the user data transmitted over the unsecured network so that unauthorized persons cannot access it . As we share the data through wireless network it should provide data confidentiality, integrity and authentication. The symmetric block cipher plays a major role in the bulk data encryption. Advanced Encryption Standard (AES) provides data security. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has lot of advantage such has increased throughput and better security level. Hardware Implementation for 128 bit AES (Advanced Encryption Standard) encryption and Decryption has been made using VHDL. The proposed algorithm for encryption and decryption module will functionally verified using modelsim, will be synthesize using Quartus 2 using Altera FPGA platform and analyze the design for the power, Throughput & area.
Keywords	AES, Encryption, Decryption, FPGA, VHDL, Security
Field	Engineering
Published In	Volume 5, Issue 2, March-April 2023
Published On	2023-03-07
Cite This	Implementation of AES Algorithm - Aasawari Ujjainkar, A. B. Kharate - IJFMR Volume 5, Issue 2, March-April 2023. DOI 10.36948/ijfmr.2023.v05i02.1766
DOI	https://doi.org/10.36948/ijfmr.2023.v05i02.1766
Short DOI	https://doi.org/grwssx

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