Design of Fault Tolerant Array Multiplier Using Parity Preserving Reversible Gate

Author(s)	Santhi Chebiyyam
Country	India
Abstract	The digital designs with Reversible logic are more popular now days because of the increased demand of low power usage. Some of the Reversible logic gates are discussed in this paper. This paper also introduces a Parity Preserving Reversible Gate (PPRG) which is used in the fault tolerant devices design such as adders, subtractors and multipliers. The design of an array multiplier by using fault tolerant parallel adders is discussed in this paper. The fault tolerant parallel adders are designed using fault tolerant full adders and half adders and these adders are designed through Parity Preserving Reversible Gate. These adders and multipliers are useful in designing complex circuits such as ALU.
Keywords	Fault Tolerant, Array Multiplier Parity Preserving, Reversible logic, Low power
Field	Engineering
Published In	Volume 5, Issue 2, March-April 2023
Published On	2023-04-18
Cite This	Design of Fault Tolerant Array Multiplier Using Parity Preserving Reversible Gate - Santhi Chebiyyam - IJFMR Volume 5, Issue 2, March-April 2023. DOI 10.36948/ijfmr.2023.v05i02.2471
DOI	https://doi.org/10.36948/ijfmr.2023.v05i02.2471
Short DOI	https://doi.org/gr5qsz

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