A Review Paper on Multi-tasking on Network on Chip(NOC)

K mamtha; K Srinivasa Rao; M Sreedhar

doi:10.36948/ijfmr.2023.v05i05.6873

A Review Paper on Multi-tasking on Network on Chip(NOC)

Author(s)	K mamtha, K Srinivasa Rao, M Sreedhar
Country	India
Abstract	Now a days development of Integrated Circuit technology is composed of multiple cores in a single chip called System on Chip (SoC). The technology has advanced from to single to multi core so as to improve the performance. These require effective communication, High performance, flexibility, scalability and design friendly interconnection. Before the initiation of Network on Chip (NoC), interconnection is based on wire and they cannot encounter ever increasing demand for on chip systems due to lack of scalability. NoC has several advantages such as high bandwidth, low power consumption and scalability. The interconnection among multiple cores on a chip have impact on communication and performance of chip design in terms of collision occurrence, noise, and pocket loss ratio and delay. Therefore, it is valuable studying the different multitasking algorithms. This paper reviews the widespread NoC algorithms and also few recent inclinations in interconnection networks. The area, power consumption, design complexity and congestion are studied to review the performance and summarize their merits.
Keywords	Network on Chip, System on Chip, Bandwidth, Multitasking, Congestion, Fault tolerant
Field	Engineering
Published In	Volume 5, Issue 5, September-October 2023
Published On	2023-09-26
Cite This	A Review Paper on Multi-tasking on Network on Chip(NOC) - K mamtha, K Srinivasa Rao, M Sreedhar - IJFMR Volume 5, Issue 5, September-October 2023. DOI 10.36948/ijfmr.2023.v05i05.6873
DOI	https://doi.org/10.36948/ijfmr.2023.v05i05.6873
Short DOI	https://doi.org/gstdbp

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A Review Paper on Multi-tasking on Network on Chip(NOC)

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