International Journal For Multidisciplinary Research

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Review on Power Reduction Technology in VLSI Multiplier

Author(s) Priti G Ingle, Amol S Baile, Shubhangi Joshi
Country India
Abstract As the demand for high-performance and energy-efficient integrated circuits continues to grow, power consumption in Very Large Scale Integration (VLSI) designs, especially in arithmetic units like multipliers, remains a critical concern. This paper presents a comprehensive review of various power reduction techniques employed in VLSI multipliers, highlighting recent advancements and key challenges in achieving lower power consumption. The review begins with an overview of the importance of power reduction in VLSI design and its impact on overall system performance. A significant portion of the paper is dedicated to circuit-level techniques, which are crucial for power reduction in VLSI multipliers. Furthermore, this review addresses the trade-offs between power reduction techniques and performance metrics such as speed and area utilization. It emphasizes the importance of carefully selecting the appropriate combination of techniques based on the specific application requirements.
Keywords Power Reduction, Low-Power Design, Power Dissipation, VLSI Multiplier, Power Optimization, Voltage Scaling, Threshold Voltage, Clock Gating, Power Gating, Multi-Threshold Voltage.
Field Engineering
Published In Volume 5, Issue 6, November-December 2023
Published On 2023-12-19
Cite This Review on Power Reduction Technology in VLSI Multiplier - Priti G Ingle, Amol S Baile, Shubhangi Joshi - IJFMR Volume 5, Issue 6, November-December 2023. DOI 10.36948/ijfmr.2023.v05i06.10532
DOI https://doi.org/10.36948/ijfmr.2023.v05i06.10532
Short DOI https://doi.org/gs9k3t
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