International Journal For Multidisciplinary Research

E-ISSN: 2582-2160   •   Impact Factor: 9.24

A Widely Indexed Open Access Peer Reviewed Multidisciplinary Bi-monthly Scholarly International Journal

Call for Paper Volume 6 Issue 6 November-December 2024 Submit your research before last 3 days of December to publish your research paper in the issue of November-December.
Submit Research Paper Join as a Reviewer

Plagiarism is checked by the leading plagiarism checker TurnItIn

Call for Paper

Volume 6 Issue 6
November-December 2024

Submit your research paper

Indexing Partners
Academia Advanced Sciences Index Bielefeld Academic Search Engine CiteSeer DRJI Google Scholar Independent Search Engine & Directory Network ISI (International Scientific Indexing) Issuu Mendeley Research Networks
RefSeek ResearcherId - Thomson Reuters ResearchGate Scirus Scribd Semantic Scholar UTeM - Universiti Teknikal Malaysia Melaka Wiki for Call for Papers WorldCat Zenodo

Optimizing Energy-Efficient in VLSI Architecture for FIR Filter in Seismic Signal Processing

Author(s) Sagar S K, Dr. J C Narayana Swamy
Country India
Abstract This project aims to developing an optimized and energy-efficient VLSI design for FIR filters specifically designed for seismic signal processing. The process begins by converting seismic signal dataset values into binary format, and then, simulating them in MATLAB, and generating a coefficient file. This coefficient file is then analyzed using Verilog HDL code and simulated in the Xilinx Vivado 2022.2 tool to assess key parameters such as area, delay, and power. The suggested architecture lessens the complexity of computing, hardware efficiency compared to traditional FIR filters that utilize the CSE technique. This design employs a critical method known as the CSD-based Matrix-Grouped Common Subexpression Elimination (MCSE) algorithm, which significantly reduces the quantity of logic operators (LOs) and logic depths (LDs). Additionally, the design incorporates a Half-Unit Biased (HUB) rounding technique to minimize the truncation errors and cut-set retiming method to reduce the critical-path delay (CPD). This hardware-efficient FIR filter constructs integrates the CSD-based MCSE algorithm, HUB rounding, and cut-set retiming techniques to offer a reconfigurable FIR filter configuration optimized for hardware efficiency, thereby enhancing the real-time alert seismic signal processing. The implementation of an Artix-7 FPGA board including clock gating techniques to further reduces the power consumption.
Keywords Finite Impulse Response (FIR), Half-Unit Biased (HUB), Canonical signed digit (CSD) based matrix groped Common Sub-Expression Elimination (MCSE), Seismic Signal, Clock Gating.
Field Engineering
Published In Volume 6, Issue 4, July-August 2024
Published On 2024-08-30
Cite This Optimizing Energy-Efficient in VLSI Architecture for FIR Filter in Seismic Signal Processing - Sagar S K, Dr. J C Narayana Swamy - IJFMR Volume 6, Issue 4, July-August 2024. DOI 10.36948/ijfmr.2024.v06i04.26712
DOI https://doi.org/10.36948/ijfmr.2024.v06i04.26712
Short DOI https://doi.org/gt8gv2
View / Download PDF File

Share this



E-ISSN 2582-2160
CrossRef

CrossRef DOI is assigned to each research paper published in our journal.

IJFMR DOI prefix is
10.36948/ijfmr

Downloads
Research Paper Format Copyright Permission Form and Undertaking Form Cover Page Vol 6 Isu 6Cover Page Vol 6 Isu 5Cover Page Vol 6 Isu 4

All research papers published on this website are licensed under Creative Commons Attribution-ShareAlike 4.0 International License, and all rights belong to their respective authors/researchers.

CC-BY-SA Open Access

About IJFMR
Fees & Payment
Current Issue
Publication Archive 		Submit Research Paper
Track Submission Status
Publication Guidelines
Publication Ethics
Peer Review & Plagiarism 		Join as a Reviewer
Editors & Reviewers
Reviewer Referral Program
Get Reviewer Membership Certi. 		Website/Journal Policies
Usage Policy
Content Policies
Privacy Policy
Contact Us +91-9898-5948-55 editor@ijfmr.com