Innovative Multi-Bit Test Pattern Generators with Variable LFSR Selection Mechanisms

Author(s)	ROOPA K R, BRUNDA s KOTIAN, Dhanya shree U, Karunya P, Shardul S
Country	India
Abstract	Test Pattern Generators is an important module for testing Asynchronous circuits that guarantee fault detection. In this paper a multi-bit TPGs with tunable LFSR lengths is presented. Our method enables smooth transitions between various word lengths by dynamically selecting LFSR configurations based on control signals. For 4-bit to 7-bit combinational circuits, we have derived a polynomial-based LFSRs and shown effect of stuck-at-fault detections through extensive testing. It includes a discussion of instructional insights regarding fault coverage and digital circuit design. By bridging fixed and flexible BIST solutions, our adaptive TPG design improves fault detection capabilities.
Keywords	BIST, TPG , LFSR ,Multi-Bit
Field	Engineering
Published In	Volume 6, Issue 5, September-October 2024
Published On	2024-10-12
Cite This	Innovative Multi-Bit Test Pattern Generators with Variable LFSR Selection Mechanisms - ROOPA K R, BRUNDA s KOTIAN, Dhanya shree U, Karunya P, Shardul S - IJFMR Volume 6, Issue 5, September-October 2024. DOI 10.36948/ijfmr.2024.v06i05.27683
DOI	https://doi.org/10.36948/ijfmr.2024.v06i05.27683
Short DOI	https://doi.org/g795g5

About IJFMR Fees & Payment Current Issue Publication Archive	Submit Research Paper Track Submission Status Publication Guidelines Publication Ethics Peer Review & Plagiarism	Join as a Reviewer Editors & Reviewers Reviewer Referral Program Get Reviewer Membership Certi.	Website/Journal Policies Usage Policy Content Policies Privacy Policy

Contact Us		+91-9898-5948-55	editor@ijfmr.com

International Journal For Multidisciplinary Research